1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and its circuit inserting method.
2. Description of the Related Art
It is a waste of power to clock drive a flip flop having no change of value and a flip flop whose output is not used for another circuit. As a method for solving this problem, a gated clock method is well known.
A schematic gated clock circuit is shown in FIG. 17. As shown in FIG. 17, the schematic gated clock circuit includes a D-type flip flop (hereinafter, it is referred to as DFF) 100 and a clock controller 101 which controls a clock line for driving the DFF. The clock controller 101 is a control circuit which transmits a clock to the DFF 100 only when an Enable signal is turned on. By turning on the Enable signal only when update of a value in the DFF is desired, power consumption can be saved.
The conventional gated clock method controls clock signals by the unit of module or in every clock domain in many cases, while in these days, they are gated-controlled minutely in every flip flop (hereinafter, referred to as FF) in order to reduce the power consumption as much as possible. This is not only to reduce the driving power of a buffer and the FF by the clock, but also to stop a wasteful driving of a combination circuit existing on the subsequent stage of the FF. An example is shown in FIGS. 18A and 18B. FIG. 18A shows an RTL (Register Transfer Level) description and FIG. 18B shows an example of a gated clock circuit according to the RTL description shown in FIG. 18A. A code shown in FIG. 18A is the RTL description for updating D only when the Enable signal is 1. The RTL is realized by the gated clock circuit as shown in FIG. 18B. By forming each FF included in the circuit as shown in FIG. 18B, it is possible to gated-control the circuit minutely in every FF. At this time, there is the following situation.
It will be described referring to FIG. 19. The circuit shown in FIG. 19 is formed by: a first DFF 200, a first combination circuit 201 to determine the value of the first DFF 200, and a first clock controller 202; a second DFF 203, a second combination circuit 204 to determine the value of the second DFF 203, and a second clock controller 205; a third DFF 206, a third combination circuit 207 to determine the value of the third DFF 206 and a third clock controller 208. The output of the first DFF 200 is connected to the second combination circuit 204 and the third combination circuit 207.
Assume that the first DFF 200 and the second DFF 203 are driven and that the third DFF 206 is stopped. That is, the first clock controller 202 and the second clock controller 205 turn on the Enable signals, and the third clock controller 208 turns off the Enable signal. As the result, the third DFF 206 and the third clock controller 208 stop their operations. However, the third combination circuit 207 to determine the value of the third DFF 206 is driven according to a change of the first DFF 200. It is wasteful that the third combination circuit 207 is driven while the third DFF 206 is stopped.
As mentioned above, when a plurality of clock domains exist, according to the gated clock technique, wasteful power may be consumed in the combination circuit portion.
As a reference about the gated clock technique, there is “Automatic Insertion of Gated Clocks at Register Transfer Level, N. Raghavan, V. Akella, S. Bakshi, Proceedings of the Twelfth International Conference on VLSI Design, 1999, pp. 48-54”.
Upon receipt of an input change, the combination circuit is driven and consumes power. Therefore, the power consumption may be reduced in the combination circuit by suppressing a wasteful input change. As the method for solving this situation, there is a guarding logic method.
A schematic guarding logic circuit is shown in FIG. 20. As shown in FIG. 20, the schematic guarding logic circuit is formed by a combination circuit 300 and an input control circuit 301 which controls an input line to the combination circuit 300. When the Enable signal is turned on, the input control circuit 301 transmits the inputs to the combination circuit 300 as they are, and when the Enable signal is turned off, it does not transmit the inputs to the combination circuit 300. Only when the outputs of the combination circuit 300 are used, the Enable signal is turned on in the input control circuit 301, hence to prevent a wasteful drive of the combination circuit 300.
When the guarding logic method is adopted, the following situations occur as a result of inserting the input control circuit 301: 1. increase of delay; 2. upsizing of circuit; and 3. necessity of an Enable signal generation circuit. They are serious problems because the increase of delay has a major effect on the operation speed of the circuit and the upsizing of circuit has a major effect on production cost of an LSI.
As a reference about the guarding logic method, there is “Guarded Evaluation: Pushing Power Management to Logic Synthesis/Design, V. Tiwari, S. Malik, P. Ashar, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 10, October 1998”.